LPDDR5/4X IP Subsystem

LPDDR5/4X IP
Subsystem

LPDDR memory are used where area and power savings are key requirements. LPDDR also offers higher bandwidth compared to DDR counterparts. LPDDR5/4X is ideally suited for next generation computing for AI Inference, Edge, IoT, Automotive and Mobile applications.

LPDDR5/4X PHY IP

LPDDR5/4X are the next generation low-power memory which boosts 2X faster data transfers than its predecessor. LPDDR devices can transfer data at higher rates with remarkable power efficiency. It also supports unique low power feature, deep sleep mode (DSM), to reduce standby power even further.

Block Diagram

LPDDR5/4X Controller and PHY

Supports all 3rd party DFI 5.0 based Controllers

Key Features

Compliant with JEDEC Standard JESD209-4B and JESD209-5
Complaint with DFI 5.0 for PHY and Controller interface
Supports data rate up to 4266Mbps for LPDDR4/4X and 6400Mbps for LPDDR5
Supports Data Bus Inversion (DBI) mode
Supports PHY independent training modes
Supports periodic re-training for DRAM write and read operation
Supports IO calibration and Programmable ODT calibration
Supports Light Sleep and Deep Sleep mode (DSM)
Supports Retention mode/Self Refresh mode (Core and IO power down)
Supports DRAM widths of x8 and x16 bits
Supports per-bit de-skew on read and write data path.
Supports 16/32/64-bit data width (Two x32, One x32 or Two x16)
Supports In-order, out-of-order and look-ahead command processing
Supports equalization for TX and RX

Download

定制

如果您已经有特定的SoC IP规格，我们的团队可以根据您的要求帮您定制控制器IP。

了解其他相关产品

我们品质一流的SoC IP应用涵盖了从IoT Devices, Networking以及AI/HPC

openfive