OpenFive Joins Universal Chiplet Interconnect Express (UCIe) Consortium

Universal Chiplet Interconnect Express (UCIe) is an open specification that defines the interconnect between chiplets within a package. The objective is to enable an open chiplet ecosystem. Although the initial specification for UCIe was developed by Intel, a consortium was announced in March with Intel, AMD, Arm, Google, Meta, Microsoft, ASE Group, Qualcomm, Samsung and TSMC as its promoting members. The promoting members represent a

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IP Subsystems and Chiplets for Edge and AI Accelerators

From a business viewpoint we often read in the technical press about the virtues of applying AI, and in the early days most of the AI model building was done in the cloud, because of the high computation requirements, yet there’s a developing trend now to use AI accelerators at the Edge. The other mega-trend in the past decade is that the RISC-V ISA has been applied

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A 2021 Summary of OpenFive

Building a better mousetrap plays a key role in achieving market success in any industry. Of course, building one requires differentiating the product from the others already in the market. A differentiated product can even lead to creating demand for new products in adjacent markets. All of this is great but how do you implement the differentiation? In the semiconductor industry, it is through a

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Interface Agnostic Universal D2D Controller for HPC and Chiplets (BoW): Part 2

Overview In our previous blog (Part 1) we discussed various interface choices for die-to-die connections. We reviewed how parallel wires are beneficial for chiplet architecture in terms of latency, throughput, and power. Following the selection of a parallel wire interface, two main technologies for parallel interfaces have emerged the past few months, based on packaging choices and throughput requirements. The first one, OHBI (Open HBI)

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RISC-V Chiplets, Disaggregated Die, and Tiles

Chris Jones, Vice President, Products—September 16, 2021 Scalable High-Performance Computing SoC Design with RISC-V Whether you refer to the design concept as a disaggregated die, tiles, chiplets, or good ol’ multi-chip modules, a growing trend among SoC designers is making the interposer act like a ‘mainboard’ to host multiple chips. Together, these chips form a coherent whole product intended for a specific market and offer

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Enabling Edge AI Vision with RISC-V and a Silicon Platform

By Tom Simon, the Moderator at SemiWiki on 03-15-2021. AI vision processing moving to the edge is an undeniable industry trend. OpenFive, the custom silicon business unit of SiFive, discusses this trend with compelling facts in their recent paper titled “Enabling AI Vision at the Edge.” AI vision is being deployed in many applications, such as autonomous vehicles, smart cities, agriculture, industrial & warehouse robotics, delivery

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Protocol and Interface Agnostic Universal D2D Controller for HPC and Chiplets

Overview Demand for die-to-die and chip-to-chip interfaces has been growing steadily in the past few years due to new applications in cloud/data centers, AI (training and edge applications), and High-Performance Computing (HPC). The demand is driven by the requirements of high throughput, low latency and low power in these applications. Advances in packaging technology are further helping the adoption of heterogeneous systems with chiplets/known-good-die(KGD) assembly to create solutions that require the evolution of

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WEBINAR: Differentiated Edge AI with OpenFive and CEVA

OpenFive is hosting a webinar with CEVA on November 12th to talk about how OpenFive’s vision platform, leveraging CEVA vision and AI solutions. Which can get you to a differentiated solution for your product with as much or as little silicon participation on your part as you want. I talked briefly to Jeff VanWashenova (CEVA Sr. Dir of AI and Computer Vision) to get a

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OpenFive’s Customizable Silicon-Focused Solutions

Today, I am excited to announce the launch of OpenFive, a self-contained and autonomous custom silicon business unit of SiFive, Inc. OpenFive is solution-centric and uniquely positioned to design processor agnostic SoCs and deliver high-quality silicon. The demand for domain-specific silicon and workload-focused architecture is driven by several key factors. General purpose processors used to be the workhorses for the majority of computing tasks. With

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Webinar: Build Your Next HBM2/2E Chip with SiFive

I have been watching the trend for quite some time now that many advanced FinFET designs today are actually 2.5D systems in package. All of these 2.5D silicon interposer-based designs have high-bandwidth memory (HBM) stacks on board. Often there are multiple memory stacks in both 4-high and 8-high configurations. If you follow what’s been called the “more than Moore” revolution associated with 2.5 and 3D

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